DSC POWER 864 - REV2 Specifikace stáhnout pdf (Strana 91)

PIC24F16KA102 FAMILY

R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0

CPUIRQ —VHOLD—ILR<3:0>

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will

happen when the CPU priority is higher than the interrupt priority)

0 = No interrupt request is left unacknowledged

bit 14 Unimplemented: Read as ‘0’

bit 13 VHOLD: Allows Vector Number Capture and Changes what Interrupt is Stored in VECNUM bit

1 = VECNUM will contain the value of the highest priority pending interrupt, instead of the current

interrupt

0 = VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred

with higher priority than the CPU, even if other interrupts are pending)

bit 12 Unimplemented: Read as ‘0’

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1

0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits

0111111 = Interrupt Vector pending is number 135

•

0000001 = Interrupt Vector pending is number 9

0000000 = Interrupt Vector pending is number 8

1 2 ... 86 87 88 89 90 91 92 93 94 95 96 ... 253 254

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DSC POWER 864 - REV2 Specifikace Strana 91